From 658e4129bb81b2a3b8c84d8f712174481e04be72 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 15 Jun 2019 12:38:32 +0200 Subject: [PATCH] arm64: dts: meson: g12b: odroid-n2: add the Ethernet PHY reset line The reset line of the RTL8211F PHY is routed to the GPIOZ_15 pad. Describe this in the device tree so the PHY framework can bring the PHY into a known state when initializing it. GPIOZ_15 doesn't support driving the output HIGH (to take the PHY out of reset, only output LOW to reset the PHY is supported). The datasheet states it's an "3.3V input tolerant open drain (OD) output pin". Instead there's a pull-up resistor on the board to take the PHY out of reset. The GPIO itself will be set to INPUT mode to take the PHY out of reset and LOW to reset the PHY, which is achieved with the flags (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN). Acked-by: Neil Armstrong Tested-by: Neil Armstrong Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts index c3e0735e6d9f9..82b42c073c5e6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts @@ -250,6 +250,10 @@ /* Realtek RTL8211F (0x001cc916) */ reg = <0>; max-speed = <1000>; + + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; }; }; -- 2.30.2