From 664b0f41ce2e8286c471fd8865d005f594733bdc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 12 Feb 2021 17:35:26 +0100 Subject: [PATCH] crypto: s5p-sss - initialize APB clock after the AXI bus clock for SlimSSS The driver for Slim Security Subsystem (SlimSSS) on Exynos5433 takes two clocks - aclk (AXI/AHB clock) and pclk (APB/Advanced Peripheral Bus clock). The "aclk", as main high speed bus clock, is enabled first. Then the "pclk" is enabled. However the driver assigned reversed names for lookup of these clocks from devicetree, so effectively the "pclk" was enabled first. Although it might not matter in reality, the correct order is to enable first main/high speed bus clock - "aclk". Also this was the intention of the actual code. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Herbert Xu --- drivers/crypto/s5p-sss.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c index 682c8a450a57b..8ed08130196f0 100644 --- a/drivers/crypto/s5p-sss.c +++ b/drivers/crypto/s5p-sss.c @@ -401,7 +401,7 @@ static const struct samsung_aes_variant exynos_aes_data = { static const struct samsung_aes_variant exynos5433_slim_aes_data = { .aes_offset = 0x400, .hash_offset = 0x800, - .clk_names = { "pclk", "aclk", }, + .clk_names = { "aclk", "pclk", }, }; static const struct of_device_id s5p_sss_dt_match[] = { -- 2.30.2