From 6913848087e29103f7062376d0ebf7efcaf1a26b Mon Sep 17 00:00:00 2001 From: James Zhu Date: Tue, 23 Jul 2019 16:45:19 -0400 Subject: [PATCH] drm/amdgpu: use VCN firmware offset for cache window Since we are using the signed FW now, and also using PSP firmware loading, but it's still potential to break driver when loading FW directly instead of PSP, so we should add offset. Signed-off-by: James Zhu Reviewed-by: Leo Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index ef8bb67844bed..0c84dbc6a62d2 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c @@ -396,11 +396,8 @@ static void vcn_v2_5_mc_resume(struct amdgpu_device *adev) WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, upper_32_bits(adev->vcn.inst[i].gpu_addr)); offset = size; - /* No signed header for now from firmware WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); - */ - WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0); } WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size); -- 2.30.2