From 6ad831ebf142ba971c5e4cb29c52b1c0c92c259b Mon Sep 17 00:00:00 2001 From: Weiwei Li Date: Wed, 15 Feb 2023 10:05:37 +0800 Subject: [PATCH] target/riscv: Fix check for vector load/store instructions when EEW=64 The V extension supports all vector load and store instructions except the V extension does not support EEW=64 for index values when XLEN=32. (Section 18.3) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Message-ID: <20230215020539.4788-13-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt --- target/riscv/insn_trans/trans_rvv.c.inc | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 9b2c5c9ac0..5dbdce073b 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -287,13 +287,12 @@ static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf, require_nf(vd, nf, s->lmul); /* - * All Zve* extensions support all vector load and store instructions, - * except Zve64* extensions do not support EEW=64 for index values - * when XLEN=32. (Section 18.2) + * V extension supports all vector load and store instructions, + * except V extension does not support EEW=64 for index values + * when XLEN=32. (Section 18.3) */ if (get_xl(s) == MXL_RV32) { - ret &= (!has_ext(s, RVV) && - s->cfg_ptr->ext_zve64f ? eew != MO_64 : true); + ret &= (eew != MO_64); } return ret; -- 2.30.2