From 70282f31f7e6b112014a1bf001affeb326e19e58 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 6 Dec 2022 12:23:28 +0100 Subject: [PATCH] arm64: dts: mt8186: Add complete CPU caches information This SoC features two clusters composed of: - 6x Cortex A55: 32KB I-cache and 32KB D-cache, 4-way set associative, per-cpu 128KB L2 cache, 4-way set associative; - 2x Cortex A76: 64KB I-cache and 64KB D-cache, 4-way set associative, per-cpu 256KB L2 cache, 8-way set associative; Moreover, the two clusters are sharing a DSU L3 cache with size 1MB, 16-way set associative. With that in mind, add the appropriate properties needed to specify the caches information for this SoC, which will now be correctly exported to sysfs. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221206112330.78431-4-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 58 ++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index 209f26f12dbc7..6321b7a440d2a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -69,6 +69,12 @@ clock-frequency = <2000000000>; capacity-dmips-mhz = <382>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; }; @@ -81,6 +87,12 @@ clock-frequency = <2000000000>; capacity-dmips-mhz = <382>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; }; @@ -93,6 +105,12 @@ clock-frequency = <2000000000>; capacity-dmips-mhz = <382>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; }; @@ -105,6 +123,12 @@ clock-frequency = <2000000000>; capacity-dmips-mhz = <382>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; }; @@ -117,6 +141,12 @@ clock-frequency = <2000000000>; capacity-dmips-mhz = <382>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; }; @@ -129,6 +159,12 @@ clock-frequency = <2000000000>; capacity-dmips-mhz = <382>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; }; @@ -141,6 +177,12 @@ clock-frequency = <2050000000>; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpu_off_b &cluster_off_b>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; next-level-cache = <&l2_1>; #cooling-cells = <2>; }; @@ -153,6 +195,12 @@ clock-frequency = <2050000000>; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpu_off_b &cluster_off_b>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; next-level-cache = <&l2_1>; #cooling-cells = <2>; }; @@ -200,18 +248,28 @@ l2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; next-level-cache = <&l3_0>; }; l2_1: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; next-level-cache = <&l3_0>; }; l3_0: l3-cache { compatible = "cache"; cache-level = <3>; + cache-size = <1048576>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-unified; }; }; -- 2.30.2