From 7265521e950ae4c0f475752ba6789688fbabfa44 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 10 Oct 2022 00:12:53 +0100 Subject: [PATCH] clk: renesas: r9a07g043: Drop WDT2 clock and reset entry WDT CH2 is specifically to check the operation of Cortex-M33 CPU and if used from CA55 CPU would result in an unexpected behaviour. Hence drop WDT2 clock and reset entries. Signed-off-by: Lad Prabhakar Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/20221009231253.15592-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g043-cpg.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 37475465100de..99f72bf590fa0 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -158,10 +158,6 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 0x548, 0), DEF_MOD("wdt0_clk", R9A07G043_WDT0_CLK, R9A07G043_OSCCLK, 0x548, 1), - DEF_MOD("wdt2_pclk", R9A07G043_WDT2_PCLK, R9A07G043_CLK_P0, - 0x548, 4), - DEF_MOD("wdt2_clk", R9A07G043_WDT2_CLK, R9A07G043_OSCCLK, - 0x548, 5), DEF_MOD("spi_clk2", R9A07G043_SPI_CLK2, R9A07G043_CLK_SPI1, 0x550, 0), DEF_MOD("spi_clk", R9A07G043_SPI_CLK, R9A07G043_CLK_SPI0, @@ -269,7 +265,6 @@ static struct rzg2l_reset r9a07g043_resets[] = { DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1), DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2), DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0), - DEF_RST(R9A07G043_WDT2_PRESETN, 0x848, 2), DEF_RST(R9A07G043_SPI_RST, 0x850, 0), DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0), DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1), -- 2.30.2