From 741f99c7ff7c508cfc0ede760ea089993b2327c3 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Niklas=20S=C3=B6derlund?= Date: Fri, 31 Mar 2023 16:14:31 +0200 Subject: [PATCH] arm64: dts: renesas: falcon-csi-dsi: Set bus-type for MAX96712 MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Specify the bus-type property for all three connected MAX96712. The default behavior when parsing a node without this property is to default to D-PHY. Making this explicit plays it safe and future proofs things as the default parsing comes from the V4L2 core and not the driver itself. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230331141431.3820311-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi index e06b8eda85e18..dbc8dcab109d1 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi @@ -5,6 +5,8 @@ * Copyright (C) 2021 Glider bv */ +#include + &csi40 { status = "okay"; @@ -105,6 +107,7 @@ port@4 { reg = <4>; max96712_out0: endpoint { + bus-type = ; clock-lanes = <0>; data-lanes = <1 2 3 4>; remote-endpoint = <&csi40_in>; @@ -125,6 +128,7 @@ port@4 { reg = <4>; max96712_out1: endpoint { + bus-type = ; clock-lanes = <0>; data-lanes = <1 2 3 4>; lane-polarities = <0 0 0 0 1>; @@ -146,6 +150,7 @@ port@4 { reg = <4>; max96712_out2: endpoint { + bus-type = ; clock-lanes = <0>; data-lanes = <1 2 3 4>; lane-polarities = <0 0 0 0 1>; -- 2.30.2