From 7678c5462680c1aba8d07926ab4d8ee906fb98cf Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Fri, 13 Dec 2019 17:15:15 +0100 Subject: [PATCH] media: cedrus: Fix decoding for some HEVC videos It seems that for some HEVC videos at least one bitstream parsing trigger must be called in order to be decoded correctly. There is no explanation why this helps, but it was observed that several videos with this fix are now decoded correctly and there is no regression with others. Without this fix, those same videos totally crash HEVC decoder (other decoder engines are unaffected). After decoding those problematic videos, HEVC decoder always returns only green image (all zeros). Only complete HW reset helps. This fix is similar to that for H264. Signed-off-by: Jernej Skrabec Acked-by: Paul Kocialkowski Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- .../staging/media/sunxi/cedrus/cedrus_h265.c | 25 ++++++++++++++++--- .../staging/media/sunxi/cedrus/cedrus_regs.h | 1 + 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c index 6945dc74e1d75..c17d30e74bb10 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c @@ -7,6 +7,7 @@ * Copyright (C) 2018 Bootlin */ +#include #include #include @@ -220,6 +221,23 @@ static void cedrus_h265_pred_weight_write(struct cedrus_dev *dev, } } +static void cedrus_h265_skip_bits(struct cedrus_dev *dev, int num) +{ + int count = 0; + + while (count < num) { + int tmp = min(num - count, 32); + + cedrus_write(dev, VE_DEC_H265_TRIGGER, + VE_DEC_H265_TRIGGER_FLUSH_BITS | + VE_DEC_H265_TRIGGER_TYPE_N_BITS(tmp)); + while (cedrus_read(dev, VE_DEC_H265_STATUS) & VE_DEC_H265_STATUS_VLD_BUSY) + udelay(1); + + count += tmp; + } +} + static void cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) { @@ -280,10 +298,9 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, /* Source offset and length in bits. */ - reg = slice_params->data_bit_offset; - cedrus_write(dev, VE_DEC_H265_BITS_OFFSET, reg); + cedrus_write(dev, VE_DEC_H265_BITS_OFFSET, 0); - reg = slice_params->bit_size - slice_params->data_bit_offset; + reg = slice_params->bit_size; cedrus_write(dev, VE_DEC_H265_BITS_LEN, reg); /* Source beginning and end addresses. */ @@ -316,6 +333,8 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, /* Initialize bitstream access. */ cedrus_write(dev, VE_DEC_H265_TRIGGER, VE_DEC_H265_TRIGGER_INIT_SWDEC); + cedrus_h265_skip_bits(dev, slice_params->data_bit_offset); + /* Bitstream parameters. */ reg = VE_DEC_H265_DEC_NAL_HDR_NAL_UNIT_TYPE(slice_params->nal_unit_type) | diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h index 7beb03d3bb391..66b152f18d17a 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h @@ -424,6 +424,7 @@ #define VE_DEC_H265_TRIGGER (VE_ENGINE_DEC_H265 + 0x34) +#define VE_DEC_H265_TRIGGER_TYPE_N_BITS(x) (((x) & 0x3f) << 8) #define VE_DEC_H265_TRIGGER_STCD_VC1 (0x02 << 4) #define VE_DEC_H265_TRIGGER_STCD_AVS (0x01 << 4) #define VE_DEC_H265_TRIGGER_STCD_HEVC (0x00 << 4) -- 2.30.2