From 77c726a4f3b124903db5ced7d597976d5b80dcfb Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Thu, 14 Sep 2023 12:30:00 +0530 Subject: [PATCH] arm64: dts: qcom: ipq9574: include the GPLL0 as clock provider for mailbox While the kernel is booting up, APSS clock / CPU clock will be running at 800MHz with GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be configured to the rate based on the opp table and the source also will be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0, with this inclusion, CPU Freq correctly reports that CPU is running at 800MHz rather than 24MHz. Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-10-c8ceb1a37680@quicinc.com [bjorn: Updated commit message, as requested by Kathiravan] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index d4b7e215fc92b..5f83ee42a7194 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -671,8 +671,8 @@ "qcom,ipq6018-apcs-apps-global"; reg = <0x0b111000 0x1000>; #clock-cells = <1>; - clocks = <&a73pll>, <&xo_board_clk>; - clock-names = "pll", "xo"; + clocks = <&a73pll>, <&xo_board_clk>, <&gcc GPLL0>; + clock-names = "pll", "xo", "gpll0"; #mbox-cells = <1>; }; -- 2.30.2