From 791b7e1dcb9fe9f9e7f7dd1b6714cd8e0f6ee349 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:35 +0000 Subject: [PATCH] arm64: dts: renesas: r9a07g054: Fillup the CANFD stub node Fillup the CANFD stub node in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 31 +++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 0b0e924e28ae6..6e89bd126788f 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -234,8 +234,37 @@ }; canfd: can@10050000 { + compatible = "renesas,r9a07g054-canfd", "renesas,rzg2l-canfd"; reg = <0 0x10050000 0 0x8000>; - /* place holder */ + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "g_err", "g_recc", + "ch0_err", "ch0_rec", "ch0_trx", + "ch1_err", "ch1_rec", "ch1_trx"; + clocks = <&cpg CPG_MOD R9A07G054_CANFD_PCLK>, + <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>; + assigned-clock-rates = <50000000>; + resets = <&cpg R9A07G054_CANFD_RSTP_N>, + <&cpg R9A07G054_CANFD_RSTC_N>; + reset-names = "rstp_n", "rstc_n"; + power-domains = <&cpg>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + channel1 { + status = "disabled"; + }; }; i2c0: i2c@10058000 { -- 2.30.2