From 79f2432e3138a3240a99441fc077181e2e8c8fb9 Mon Sep 17 00:00:00 2001 From: Matt Roper Date: Wed, 19 Apr 2023 15:49:09 -0700 Subject: [PATCH] drm/xe/sr: Apply masked registers properly The 'clear' field for register save/restore entries was being placed in the value bits of the register rather than the mask bits; make sure it gets shifted into the mask bits. Cc: Lucas De Marchi Cc: Matt Atwood Reviewed-by: Matt Atwood Reviewed-by: Lucas De Marchi Link: https://lore.kernel.org/r/20230419224909.4000920-1-matthew.d.roper@intel.com Signed-off-by: Matt Roper Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/xe/xe_reg_sr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xe/xe_reg_sr.c b/drivers/gpu/drm/xe/xe_reg_sr.c index ff83da4cf4a76..e38397fc771a1 100644 --- a/drivers/gpu/drm/xe/xe_reg_sr.c +++ b/drivers/gpu/drm/xe/xe_reg_sr.c @@ -148,7 +148,7 @@ static void apply_one_mmio(struct xe_gt *gt, u32 reg, * supposed to set all bits. */ if (entry->masked_reg) - val = (entry->clr_bits ?: entry->set_bits << 16); + val = (entry->clr_bits ?: entry->set_bits) << 16; else if (entry->clr_bits + 1) val = (entry->reg_type == XE_RTP_REG_MCR ? xe_gt_mcr_unicast_read_any(gt, MCR_REG(reg)) : -- 2.30.2