From 7aa8a266aaa25e9e2f85d9d2d594cdff6b5635f2 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Wed, 6 Jul 2022 13:50:45 +0530 Subject: [PATCH] drm/amdgpu: Fix GRBM programming sequence It needs to be done only for XCC instances in non-AID0. Use the physical instance to determine non-AID0 XCC instances. Signed-off-by: Lijo Lazar Reviewed-by: Le Ma Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index e9c12b4970f97..43126f7b70eac 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -186,11 +186,14 @@ static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) { - int i, num_xcc; + int i, num_xcc, dev_inst; num_xcc = NUM_XCC(adev->gfx.xcc_mask); - for (i = 2; i < num_xcc; i++) - WREG32_SOC15(GC, GET_INST(GC, i), regGRBM_MCM_ADDR, 0x4); + for (i = 0; i < num_xcc; i++) { + dev_inst = GET_INST(GC, i); + if (dev_inst >= 2) + WREG32_SOC15(GC, dev_inst, regGRBM_MCM_ADDR, 0x4); + } } static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, -- 2.30.2