From 8389b869bbf00de11e5bc7ae3a433eb13d7b53d0 Mon Sep 17 00:00:00 2001 From: Marc Gonzalez Date: Mon, 1 Apr 2019 17:40:13 +0200 Subject: [PATCH] arm64: dts: qcom: msm8998: Add ANOC1 SMMU node The MSM8998 ANOC1(*) SMMU services BLSP2, PCIe, UFS, and USB. (*) Aggregate Network-on-Chip #1 Based on the following DTS downstream: https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm-arm-smmu-8998.dtsi?h=LE.UM.1.3.r3.25#n18 Signed-off-by: Marc Gonzalez Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 1814ec1a15d03..cc2f83a534895 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -859,6 +859,21 @@ #thermal-sensor-cells = <1>; }; + anoc1_smmu: iommu@1680000 { + compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; + reg = <0x01680000 0x10000>; + #iommu-cells = <1>; + + #global-interrupts = <0>; + interrupts = + , + , + , + , + , + ; + }; + tcsr_mutex_regs: syscon@1f40000 { compatible = "syscon"; reg = <0x1f40000 0x20000>; -- 2.30.2