From 8bcbcdb7293cc24eb7b24b67ef2b29b3a45a49e0 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 15 Aug 2020 20:22:23 +0200 Subject: [PATCH] ARM: dts: meson: move the L2 cache-controller inside the SoC node All IO mapped SoC peripherals should be within the "soc" node. Move the L2 cache-controller there as well since it's the only one not following this pattern. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman Tested-by: Kevin Hilman Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20200815182223.408965-1-martin.blumenstingl@googlemail.com --- arch/arm/boot/dts/meson.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index eadb0832bcfc9..7649dd1e0b9ee 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -11,13 +11,6 @@ #size-cells = <1>; interrupt-parent = <&gic>; - L2: cache-controller@c4200000 { - compatible = "arm,pl310-cache"; - reg = <0xc4200000 0x1000>; - cache-unified; - cache-level = <2>; - }; - soc { compatible = "simple-bus"; #address-cells = <1>; @@ -172,6 +165,13 @@ }; }; + L2: cache-controller@c4200000 { + compatible = "arm,pl310-cache"; + reg = <0xc4200000 0x1000>; + cache-unified; + cache-level = <2>; + }; + periph: bus@c4300000 { compatible = "simple-bus"; reg = <0xc4300000 0x10000>; -- 2.30.2