From 938dd05ea1f3a9e3c713b1d73dc2992d62efb830 Mon Sep 17 00:00:00 2001 From: "demin.han" Date: Mon, 26 Feb 2024 01:41:14 +0800 Subject: [PATCH] target/riscv: Fix shift count overflow The result of (8 - 3 - vlmul) is negative when vlmul >= 6, and results in wrong vill. Signed-off-by: demin.han Reviewed-by: Daniel Henrique Barboza Message-ID: <20240225174114.5298-1-demin.han@starfivetech.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 84cec73eb2..fe56c007d5 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -44,6 +44,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, target_ulong reserved = s2 & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT, xlen - 1 - R_VTYPE_RESERVED_SHIFT); + uint16_t vlen = cpu->cfg.vlenb << 3; int8_t lmul; if (vlmul & 4) { @@ -53,10 +54,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, * VLEN * LMUL >= SEW * VLEN >> (8 - lmul) >= sew * (vlenb << 3) >> (8 - lmul) >= sew - * vlenb >> (8 - 3 - lmul) >= sew */ - if (vlmul == 4 || - cpu->cfg.vlenb >> (8 - 3 - vlmul) < sew) { + if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) { vill = true; } } -- 2.30.2