From 94ae11885fae1717f2017cb96ceef5d0f6d6dd4a Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Tue, 29 Nov 2022 09:44:57 +0000 Subject: [PATCH] media: rzg2l-cru: fix a test for timeout The test for if the loop timed out is wrong and Smatch complains: drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c:411 rzg2l_csi2_mipi_link_disable() warn: should this be 'timeout == -1' Let's change it to a preop loop instead of a post op loop. Fixes: 51e8415e39a9 ("media: platform: Add Renesas RZ/G2L MIPI CSI-2 receiver driver") Signed-off-by: Dan Carpenter Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c index 3deb09be64001..33e08efa3039c 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c @@ -402,7 +402,7 @@ static void rzg2l_csi2_mipi_link_disable(struct rzg2l_csi2 *csi2) rzg2l_csi2_write(csi2, CSI2nRTCT, CSI2nRTCT_VSRST); /* Make sure CSI2nRTST.VSRSTS bit is cleared */ - while (timeout--) { + while (--timeout) { if (!(rzg2l_csi2_read(csi2, CSI2nRTST) & CSI2nRTST_VSRSTS)) break; usleep_range(100, 200); -- 2.30.2