From a56035c95ec6b55746528a107a4dcdeb8bac0147 Mon Sep 17 00:00:00 2001 From: Anshuman Khandual Date: Wed, 14 Jun 2023 12:29:48 +0530 Subject: [PATCH] arm64/sysreg: Convert TRBTRG_EL1 register to automatic generation This converts TRBTRG_EL1 register to automatic generation without causing any functional change. Cc: Will Deacon Cc: Marc Zyngier Cc: Mark Brown Cc: Rob Herring Cc: Suzuki K Poulose Cc: James Morse Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Mark Brown Signed-off-by: Anshuman Khandual Reviewed-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20230614065949.146187-14-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas --- arch/arm64/include/asm/sysreg.h | 3 --- arch/arm64/tools/sysreg | 5 +++++ 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 8d599f579c816..d466791058061 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -227,13 +227,10 @@ /*** End of Statistical Profiling Extension ***/ -#define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6) #define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7) #define TRBSR_EL1_BSC_MASK GENMASK(5, 0) #define TRBSR_EL1_BSC_SHIFT 0 -#define TRBTRG_EL1_TRG_MASK GENMASK(31, 0) -#define TRBTRG_EL1_TRG_SHIFT 0 #define TRBIDR_EL1_F BIT(5) #define TRBIDR_EL1_P BIT(4) #define TRBIDR_EL1_Align_MASK GENMASK(3, 0) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 8464d364cba1c..26da20f3ff40b 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2314,3 +2314,8 @@ Enum 9:8 SH EndEnum Field 7:0 Attr EndSysreg + +Sysreg TRBTRG_EL1 3 0 9 11 6 +Res0 63:32 +Field 31:0 TRG +EndSysreg -- 2.30.2