From a77a1e2f1b00ec3385523283b8fcbd56ed166797 Mon Sep 17 00:00:00 2001 From: Doug Brown Date: Sun, 12 Jun 2022 12:29:27 -0700 Subject: [PATCH] clk: mmp: pxa168: fix incorrect dividers These two clocks had multipliers and dividers that didn't match their names. A subsequent commit goes through all of the existing peripherals and ensure the correct clocks are being used everywhere. Signed-off-by: Doug Brown Link: https://lore.kernel.org/r/20220612192937.162952-3-doug@schmorgal.com Signed-off-by: Stephen Boyd --- drivers/clk/mmp/clk-of-pxa168.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mmp/clk-of-pxa168.c b/drivers/clk/mmp/clk-of-pxa168.c index 513942f9f5ed3..88b5200262d9c 100644 --- a/drivers/clk/mmp/clk-of-pxa168.c +++ b/drivers/clk/mmp/clk-of-pxa168.c @@ -88,8 +88,8 @@ static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = { {PXA168_CLK_PLL1_96, "pll1_96", "pll1_48", 1, 2, 0}, {PXA168_CLK_PLL1_192, "pll1_192", "pll1_96", 1, 2, 0}, {PXA168_CLK_PLL1_13, "pll1_13", "pll1", 1, 13, 0}, - {PXA168_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 2, 3, 0}, - {PXA168_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 2, 3, 0}, + {PXA168_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 1, 5, 0}, + {PXA168_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 1, 5, 0}, {PXA168_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0}, }; -- 2.30.2