From ac6bcf4d467a091b11ece782f4bf0a41e0f59cef Mon Sep 17 00:00:00 2001 From: LIU Zhiwei Date: Tue, 1 Feb 2022 14:46:01 +0800 Subject: [PATCH] target/riscv: Fix vill field write in vtype The guest should be able to set the vill bit as part of vsetvl. Currently we may set env->vill to 1 in the vsetvl helper, but there is nowhere that we set it to 0, so once it transitions to 1 it's stuck there until the system is reset. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20220201064601.41143-1-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 020d2e841f..3bd4aac9c9 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -71,6 +71,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, env->vl = vl; env->vtype = s2; env->vstart = 0; + env->vill = 0; return vl; } -- 2.30.2