From b0f8a6d5ef0e5d37176e4ce8e297bfffb7438503 Mon Sep 17 00:00:00 2001 From: Gavin Wan Date: Thu, 21 May 2020 19:35:28 +0000 Subject: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. For SRIOV, since the CP_INT_CNTL_RING0 is programed on host side. The Guest should not program CP_INT_CNTL_RING0 again. Signed-off-by: Gavin Wan Reviewed-by: Monk Liu Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 19de77cea8900..df2d2f609d0b8 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4558,7 +4558,12 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, bool enable) { - u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); + u32 tmp; + + if (amdgpu_sriov_vf(adev)) + return; + + tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); -- 2.30.2