From b72633ba5cfa932405832de25d0f0a11716903b4 Mon Sep 17 00:00:00 2001 From: Dragan Simic Date: Fri, 15 Dec 2023 06:00:33 +0100 Subject: [PATCH] arm64: dts: rockchip: Add cache information to the SoC dtsi for RK3399 Add missing cache information to the Rockchip RK3399 SoC dtsi. The specified values were derived by hand from the cache size specifications available from the RK3399 datasheet; for future reference, here's a brief summary: - Each Cortex-A72 core has 48 KB of L1 instruction cache and 32 KB of L1 data cache available, four-way set associative - Each Cortex-A53 core core has 32 KB of instruction cache and 32 KB of L1 data cache available, four-way set associative - The big (A72) cluster has 1 MB of unified L2 cache available - The little (A53) cluster has 512 KB of unified L2 cache available This patch allows /proc/cpuinfo and lscpu(1) to display proper RK3399 cache information, and it eliminates the following error in the kernel log: cacheinfo: Unable to detect cache hierarchy for CPU 0 While there, add a couple of somewhat useful comments, which may help a bit anyone going through the RK3399 SoC dtsi. Co-developed-by: Kyle Copperfield Signed-off-by: Kyle Copperfield Signed-off-by: Dragan Simic Link: https://lore.kernel.org/r/be3cbcae5c40fa72a52845d30dcc66c847a98cfa.1702616304.git.dsimic@manjaro.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 64 +++++++++++++++++++++++- 1 file changed, 62 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 6e12c5a920cab..33d38d653a0a3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -45,7 +45,7 @@ #size-cells = <0>; cpu-map { - cluster0 { + cluster0 { /* Cortex-A53 */ core0 { cpu = <&cpu_l0>; }; @@ -60,7 +60,7 @@ }; }; - cluster1 { + cluster1 { /* Cortex-A72 */ core0 { cpu = <&cpu_b0>; }; @@ -80,6 +80,13 @@ #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l>; }; cpu_l1: cpu@1 { @@ -92,6 +99,13 @@ #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l>; }; cpu_l2: cpu@2 { @@ -104,6 +118,13 @@ #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l>; }; cpu_l3: cpu@3 { @@ -116,6 +137,13 @@ #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l>; }; cpu_b0: cpu@100 { @@ -128,6 +156,13 @@ #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <436>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b>; thermal-idle { #cooling-cells = <2>; @@ -146,6 +181,13 @@ #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <436>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b>; thermal-idle { #cooling-cells = <2>; @@ -154,6 +196,24 @@ }; }; + l2_cache_l: l2-cache-cluster0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + }; + + l2_cache_b: l2-cache-cluster1 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; + }; + idle-states { entry-method = "psci"; -- 2.30.2