From b8bf63f8eb728dc9cb0ae0ee921eb889a11186cb Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Fri, 2 Dec 2022 07:09:18 -0500 Subject: [PATCH] arm64: dts: qcom: sa8540p-ride: enable PCIe support Add the vreg_l11a, pcie3a, pcie3a_phy, and tlmm nodes that are necessary in order to get PCIe working on the QDrive3. This patch also increases the width of the ranges property for the PCIe switch that's found on this platform. Note that this change requires the latest trustzone (TZ) firmware that's available from Qualcomm as of November 2022. If this is used against a board with the older firmware, then the board will go into ramdump mode when PCIe is probed on startup. The ranges property is overridden in this sa8540p-ride.dts file since this is what's used to describe the QDrive3 variant with dual SoCs. There's another variant of this board that only has a single SoC where this change is not applicable, and hence why this specific change was not done in sa8540p.dtsi. These changes were derived from various patches that Qualcomm delivered to Red Hat in a downstream kernel. Signed-off-by: Brian Masney Tested-by: Andrew Halaney Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221202120918.2252647-1-bmasney@redhat.com --- arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 53 +++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index a5f87a8629d61..6c547f1b13dc4 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -51,6 +51,13 @@ regulator-initial-mode = ; }; + vreg_l11a: ldo11 { + regulator-name = "vreg_l11a"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + vreg_l13a: ldo13 { regulator-name = "vreg_l13a"; regulator-min-microvolt = <3072000>; @@ -139,6 +146,27 @@ }; }; +&pcie3a { + ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x20000000>, + <0x03000000 0x6 0x00000000 0x6 0x00000000 0x2 0x00000000>; + + perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie3a_default>; + + status = "okay"; +}; + +&pcie3a_phy { + vdda-phy-supply = <&vreg_l11a>; + vdda-pll-supply = <&vreg_l3a>; + + status = "okay"; +}; + &qup2 { status = "okay"; }; @@ -158,6 +186,31 @@ status = "okay"; }; +&tlmm { + pcie3a_default: pcie3a-default-state { + perst-pins { + pins = "gpio151"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio150"; + function = "pcie3a_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio56"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + &ufs_mem_hc { reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>; -- 2.30.2