From bb8557359806dde16191060cf27d5dd79eaf11d9 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Wed, 14 Jul 2021 01:25:07 +0200 Subject: [PATCH] clk: meson: meson8b: Add the HDMI PLL M/N parameters The 3.10 vendor kernel uses only specific HDMI PLL M/N parameter combinations. The PLL won't lock for values smaller than 50 if the internal doubling (which is yet unknown how to use it) is disabled. However, when this doubling is enabled then the values smaller than 50 will lock just fine. The only restriction for values greater than 50 is that the resulting frequency must not exceed the 3.0GHz limit. These values are taken from the endlessm 3.10 kernel which includes additional M/N combinations for some VESA and 75Hz display modes. Signed-off-by: Martin Blumenstingl Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20210713232510.3057750-4-martin.blumenstingl@googlemail.com --- drivers/clk/meson/meson8b.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 9ccffbfe44e56..8f29d26ed726e 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -118,6 +118,27 @@ static struct clk_regmap meson8b_fixed_pll = { }, }; +static const struct pll_params_table hdmi_pll_params_table[] = { + PLL_PARAMS(40, 1), + PLL_PARAMS(42, 1), + PLL_PARAMS(44, 1), + PLL_PARAMS(45, 1), + PLL_PARAMS(49, 1), + PLL_PARAMS(52, 1), + PLL_PARAMS(54, 1), + PLL_PARAMS(56, 1), + PLL_PARAMS(59, 1), + PLL_PARAMS(60, 1), + PLL_PARAMS(61, 1), + PLL_PARAMS(62, 1), + PLL_PARAMS(64, 1), + PLL_PARAMS(66, 1), + PLL_PARAMS(68, 1), + PLL_PARAMS(71, 1), + PLL_PARAMS(82, 1), + { /* sentinel */ } +}; + static struct clk_regmap meson8b_hdmi_pll_dco = { .data = &(struct meson_clk_pll_data){ .en = { @@ -150,6 +171,7 @@ static struct clk_regmap meson8b_hdmi_pll_dco = { .shift = 29, .width = 1, }, + .table = hdmi_pll_params_table, }, .hw.init = &(struct clk_init_data){ /* sometimes also called "HPLL" or "HPLL PLL" */ -- 2.30.2