From bd2912f400934d71ecb040f625685b886ccdcc20 Mon Sep 17 00:00:00 2001 From: Nitin Yadav Date: Thu, 12 Jan 2023 17:28:44 +0100 Subject: [PATCH] arm64: dts: ti: k3-am62-main: Update OTAP and ITAP delay select UHS Class U1 sd-card are not getting detected due to incorrect OTAP/ITAP delay select values in linux. Update OTAP and ITAP delay select values for various speed modes. For sdhci0, update OTAP delay values for ddr52 & HS200 and add ITAP delay for legacy & mmc-hs. For sdhci1 & sdhci2, update OTAP & ITAP delay select recommended as in RIOT for various speed modes. Signed-off-by: Nitin Yadav [cherry-pick from vendor BSP] Signed-off-by: Sjoerd Simons Tested-by: Martyn Welch Signed-off-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20230112162847.973869-2-sjoerd@collabora.com --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 46 ++++++++++++------------ 1 file changed, 24 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index ae1ec58117c35..f1dfeb2823325 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -501,8 +501,10 @@ ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; - ti,otap-del-sel-ddr52 = <0x9>; - ti,otap-del-sel-hs200 = <0x6>; + ti,otap-del-sel-ddr52 = <0x5>; + ti,otap-del-sel-hs200 = <0x5>; + ti,itap-del-sel-legacy = <0xa>; + ti,itap-del-sel-mmc-hs = <0x1>; status = "disabled"; }; @@ -514,17 +516,17 @@ clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; clock-names = "clk_ahb", "clk_xin"; ti,trm-icp = <0x2>; - ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-legacy = <0x8>; ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0xf>; - ti,otap-del-sel-sdr25 = <0xf>; - ti,otap-del-sel-sdr50 = <0xc>; - ti,otap-del-sel-sdr104 = <0x6>; - ti,otap-del-sel-ddr50 = <0x9>; - ti,itap-del-sel-legacy = <0x0>; - ti,itap-del-sel-sd-hs = <0x0>; - ti,itap-del-sel-sdr12 = <0x0>; - ti,itap-del-sel-sdr25 = <0x0>; + ti,otap-del-sel-sdr12 = <0x0>; + ti,otap-del-sel-sdr25 = <0x0>; + ti,otap-del-sel-sdr50 = <0x8>; + ti,otap-del-sel-sdr104 = <0x7>; + ti,otap-del-sel-ddr50 = <0x4>; + ti,itap-del-sel-legacy = <0xa>; + ti,itap-del-sel-sd-hs = <0x1>; + ti,itap-del-sel-sdr12 = <0xa>; + ti,itap-del-sel-sdr25 = <0x1>; ti,clkbuf-sel = <0x7>; bus-width = <4>; status = "disabled"; @@ -538,17 +540,17 @@ clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; clock-names = "clk_ahb", "clk_xin"; ti,trm-icp = <0x2>; - ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-legacy = <0x8>; ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0xf>; - ti,otap-del-sel-sdr25 = <0xf>; - ti,otap-del-sel-sdr50 = <0xc>; - ti,otap-del-sel-sdr104 = <0x6>; - ti,otap-del-sel-ddr50 = <0x9>; - ti,itap-del-sel-legacy = <0x0>; - ti,itap-del-sel-sd-hs = <0x0>; - ti,itap-del-sel-sdr12 = <0x0>; - ti,itap-del-sel-sdr25 = <0x0>; + ti,otap-del-sel-sdr12 = <0x0>; + ti,otap-del-sel-sdr25 = <0x0>; + ti,otap-del-sel-sdr50 = <0x8>; + ti,otap-del-sel-sdr104 = <0x7>; + ti,otap-del-sel-ddr50 = <0x8>; + ti,itap-del-sel-legacy = <0xa>; + ti,itap-del-sel-sd-hs = <0xa>; + ti,itap-del-sel-sdr12 = <0xa>; + ti,itap-del-sel-sdr25 = <0x1>; ti,clkbuf-sel = <0x7>; status = "disabled"; }; -- 2.30.2