From c2e9012bb383f538186cf11d00d223d025d10c8d Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Mon, 6 Mar 2023 16:13:54 +0100 Subject: [PATCH] arm64: dts: amlogic: gxl: use gxl mdio multiplexer So the far, GXL SoCs were using the generic mmio register based mdio multiplexer. This properly sets one of the glue register but the SoC actually has 3 of those registers. One of them sets the ID under which the internal phy will advertise itself. If nothing sets this register before linux boots (like u-boot), the internal phy path is broken. To address this problem, a dedicated MDIO mux driver has been introduced. Switch to this new driver. Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20230306151354.132973-1-jbrunet@baylibre.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 25 +++++++++++----------- 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index 6f3c2bc36919f..17bcfa4702e17 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -773,16 +773,23 @@ }; }; - eth-phy-mux@55c { - compatible = "mdio-mux-mmioreg", "mdio-mux"; + eth_phy_mux: mdio@558 { + reg = <0x0 0x558 0x0 0xc>; + compatible = "amlogic,gxl-mdio-mux"; #address-cells = <1>; #size-cells = <0>; - reg = <0x0 0x55c 0x0 0x4>; - mux-mask = <0xffffffff>; + clocks = <&clkc CLKID_FCLK_DIV4>; + clock-names = "ref"; mdio-parent-bus = <&mdio0>; - internal_mdio: mdio@e40908ff { - reg = <0xe40908ff>; + external_mdio: mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + internal_mdio: mdio@1 { + reg = <0x1>; #address-cells = <1>; #size-cells = <0>; @@ -793,12 +800,6 @@ max-speed = <100>; }; }; - - external_mdio: mdio@2009087f { - reg = <0x2009087f>; - #address-cells = <1>; - #size-cells = <0>; - }; }; }; -- 2.30.2