From c506fe31d7220b088abd9312867849bc2ecf3f51 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 2 May 2023 15:35:43 +0200 Subject: [PATCH] arm64: zynqmp: Add pinctrl emmc description to SM-K26 Production SOM has emmc on it and make sense to describe pin description to be able use EMMC if it is not configured via psu_init. (Still some regs are not handled but this is one step in that direction) Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/f61c16e2fd7c91c2be6d6b67c902037580dbd364.1683034376.git.michal.simek@amd.com --- .../boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index 583a2d533cef9..dbc595c2d56b5 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -14,6 +14,7 @@ #include #include #include +#include / { model = "ZynqMP SM-K26 Rev1/B/A"; @@ -85,6 +86,23 @@ status = "okay"; }; +&pinctrl0 { + status = "okay"; + pinctrl_sdhci0_default: sdhci0-default { + conf { + groups = "sdio0_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + + mux { + groups = "sdio0_0_grp"; + function = "sdio0"; + }; + }; +}; + &qspi { /* MIO 0-5 - U143 */ status = "okay"; spi_flash: flash@0 { /* MT25QU512A */ @@ -182,6 +200,8 @@ &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */ status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci0_default>; non-removable; disable-wp; bus-width = <8>; -- 2.30.2