From d6dabaf678971733da56b2e84793348f714d42ff Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 12 Nov 2021 08:10:01 +0000 Subject: [PATCH] clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV Core clock "I" is sourced from CPG_PL1_DDIV divider as per HW manual Rev.1.00. This patch adds clock divider table "dtable_1_8" and switches to DEF_DIV for "I" clock. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211112081003.15453-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g044-cpg.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 6c0c95be70903..02c4d0b9d7e51 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -56,6 +56,14 @@ enum clk_ids { }; /* Divider tables */ +static const struct clk_div_table dtable_1_8[] = { + {0, 1}, + {1, 2}, + {2, 4}, + {3, 8}, + {0, 0}, +}; + static const struct clk_div_table dtable_1_32[] = { {0, 1}, {1, 2}, @@ -110,7 +118,8 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2), /* Core output clk */ - DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1), + DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8, + CLK_DIVIDER_HIWORD_MASK), DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2), -- 2.30.2