From d7d87484bea9a8fd25f58f045b371a6be5c354a9 Mon Sep 17 00:00:00 2001 From: =?utf8?q?M=C3=A5rten=20Lindahl?= Date: Mon, 20 Dec 2021 12:30:23 +0100 Subject: [PATCH] dt-bindings: mmc: exynos-dw-mshc: Add support for ARTPEC-8 MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The ARTPEC-8 SoC has a DWMMC controller that is compatible with the Exynos 7 version v2.70a. The main differences from Exynos 7 is that it does not support HS400 and has extended data read timeout. Add compatibility string "axis,artpec8-dw-mshc" for ARTPEC-8. Signed-off-by: MÃ¥rten Lindahl Reviewed-by: Krzysztof Kozlowski Acked-by: Rob Herring Link: https://lore.kernel.org/r/20211220113026.21129-2-marten.lindahl@axis.com Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt index 0419a63f73a01..753e9d7d89564 100644 --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt @@ -22,6 +22,8 @@ Required Properties: specific extensions. - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7 specific extensions having an SMU. + - "axis,artpec8-dw-mshc": for controllers with ARTPEC-8 specific + extensions. * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface unit (ciu) clock. This property is applicable only for Exynos5 SoC's and -- 2.30.2