From d863492886930a1a6f7c0d9dda8f728077b540f0 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Otto=20Pfl=C3=BCger?= Date: Wed, 2 Aug 2023 19:03:18 +0200 Subject: [PATCH] clk: qcom: gcc-msm8917: Enable GPLL0_SLEEP_CLK_SRC MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit This is the parent clock of gpll0_early, so it needs to be enabled for gpll0_early to return the correct rate. Enable GPLL0_SLEEP_CLK_SRC by adding its existing definition to the clock list. This clock also doesn't work with clk_alpha_pll_ops, use clk_branch_simple_ops instead to make it enable and disable correctly. Signed-off-by: Otto Pflüger Link: https://lore.kernel.org/r/20230802170317.205112-3-otto.pflueger@abscue.de Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-msm8917.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-msm8917.c b/drivers/clk/qcom/gcc-msm8917.c index a4c33a2ce61ca..b2cbdb351fcf9 100644 --- a/drivers/clk/qcom/gcc-msm8917.c +++ b/drivers/clk/qcom/gcc-msm8917.c @@ -64,7 +64,7 @@ static struct clk_alpha_pll gpll0_sleep_clk_src = { .index = DT_XO, }, .num_parents = 1, - .ops = &clk_alpha_pll_ops, + .ops = &clk_branch_simple_ops, }, }, }; @@ -3042,6 +3042,7 @@ static struct gdsc cpp_gdsc = { static struct clk_regmap *gcc_msm8917_clocks[] = { [GPLL0] = &gpll0.clkr, [GPLL0_EARLY] = &gpll0_early.clkr, + [GPLL0_SLEEP_CLK_SRC] = &gpll0_sleep_clk_src.clkr, [GPLL3] = &gpll3.clkr, [GPLL3_EARLY] = &gpll3_early.clkr, [GPLL4] = &gpll4.clkr, -- 2.30.2