From dc22aa130565acc4952a13378c782a95cf82b193 Mon Sep 17 00:00:00 2001 From: Vandita Kulkarni Date: Tue, 20 Jul 2021 12:19:07 +0530 Subject: [PATCH] drm/i915/display/dsc: Force dsc BPP Set DSC BPP to the value forced through debugfs. It can go from bpc to bpp-1. v2: Use default dsc bpp when we are just doing force_dsc_en, use default dsc bpp for invalid force_dsc_bpp values. (Jani) Signed-off-by: Vandita Kulkarni Reviewed-by: Swati Sharma Link: https://patchwork.freedesktop.org/patch/msgid/20210720064907.9771-4-vandita.kulkarni@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 5b52beaddada0..c386ef8eb2006 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1274,6 +1274,23 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, pipe_config->pipe_bpp); pipe_config->dsc.slice_count = dsc_dp_slice_count; } + + /* As of today we support DSC for only RGB */ + if (intel_dp->force_dsc_bpp) { + if (intel_dp->force_dsc_bpp >= 8 && + intel_dp->force_dsc_bpp < pipe_bpp) { + drm_dbg_kms(&dev_priv->drm, + "DSC BPP forced to %d", + intel_dp->force_dsc_bpp); + pipe_config->dsc.compressed_bpp = + intel_dp->force_dsc_bpp; + } else { + drm_dbg_kms(&dev_priv->drm, + "Invalid DSC BPP %d", + intel_dp->force_dsc_bpp); + } + } + /* * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate * is greater than the maximum Cdclock and if slice count is even -- 2.30.2