From de332bf242787dc39b0cf4493dc989d6d9fdce93 Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Wed, 2 Dec 2020 13:33:37 +0800 Subject: [PATCH] clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 bypass clocks This patch adds SCU clocks support for i.MX8qxp DC0 subsystem bypass clocks. Cc: Michael Turquette Cc: Stephen Boyd Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: Dong Aisheng Cc: Rob Herring Signed-off-by: Liu Ying Signed-off-by: Shawn Guo --- drivers/clk/imx/clk-imx8qxp.c | 2 ++ include/dt-bindings/clock/imx8-clock.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index b48643e42e8a6..af6a5454ad49f 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -119,6 +119,8 @@ static int imx8qxp_clk_probe(struct platform_device *pdev) clks[IMX_DC0_DISP1_CLK] = imx_clk_scu("dc0_disp1_clk", IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1, clk_cells); clks[IMX_DC0_PLL0_CLK] = imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL, clk_cells); clks[IMX_DC0_PLL1_CLK] = imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL, clk_cells); + clks[IMX_DC0_BYPASS0_CLK] = imx_clk_scu("dc0_bypass0_clk", IMX_SC_R_DC_0_VIDEO0, IMX_SC_PM_CLK_BYPASS, clk_cells); + clks[IMX_DC0_BYPASS1_CLK] = imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS, clk_cells); /* MIPI-LVDS SS */ clks[IMX_MIPI0_I2C0_CLK] = imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells); diff --git a/include/dt-bindings/clock/imx8-clock.h b/include/dt-bindings/clock/imx8-clock.h index 673a8c6623400..82b1fc8d1ee0f 100644 --- a/include/dt-bindings/clock/imx8-clock.h +++ b/include/dt-bindings/clock/imx8-clock.h @@ -64,6 +64,8 @@ #define IMX_DC0_PLL1_CLK 81 #define IMX_DC0_DISP0_CLK 82 #define IMX_DC0_DISP1_CLK 83 +#define IMX_DC0_BYPASS0_CLK 84 +#define IMX_DC0_BYPASS1_CLK 85 /* MIPI-LVDS SS */ #define IMX_MIPI_IPG_CLK 90 -- 2.30.2