From e49db376345290eeaed696557fa432b2420c7216 Mon Sep 17 00:00:00 2001 From: Tom St Denis Date: Thu, 4 Mar 2021 10:52:09 -0500 Subject: [PATCH] drm/amd/amdgpu: Add missing BASE_IDX to dcn register The register mmOTG1_OTG_BLANK_CONTROL was missing BASE_IDX value. Signed-off-by: Tom St Denis Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h index cf166b591bc5d..483769fb1736b 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h @@ -8922,7 +8922,7 @@ #define mmOTG1_OTG_CONTROL 0x1bc1 #define mmOTG1_OTG_CONTROL_BASE_IDX 2 #define mmOTG1_OTG_BLANK_CONTROL 0x1bc2 -#define mmOTG1_OTG_BLANK_CONTROL_BASE_IDX +#define mmOTG1_OTG_BLANK_CONTROL_BASE_IDX 2 #define mmOTG1_OTG_INTERLACE_CONTROL 0x1bc4 #define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2 #define mmOTG1_OTG_INTERLACE_STATUS 0x1bc5 -- 2.30.2