From f0d4627f645924edd855a3242ce4f2cdc3d61126 Mon Sep 17 00:00:00 2001 From: Anshuman Khandual Date: Wed, 14 Jun 2023 12:29:49 +0530 Subject: [PATCH] arm64/sysreg: Convert TRBIDR_EL1 register to automatic generation This converts TRBIDR_EL1 register to automatic generation without causing any functional change. Cc: Will Deacon Cc: Marc Zyngier Cc: Mark Brown Cc: Rob Herring Cc: Suzuki K Poulose Cc: James Morse Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Mark Brown Signed-off-by: Anshuman Khandual Reviewed-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20230614065949.146187-15-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas --- arch/arm64/include/asm/sysreg.h | 6 ------ arch/arm64/tools/sysreg | 13 +++++++++++++ 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index d466791058061..0c07b03d511f7 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -227,14 +227,8 @@ /*** End of Statistical Profiling Extension ***/ -#define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7) - #define TRBSR_EL1_BSC_MASK GENMASK(5, 0) #define TRBSR_EL1_BSC_SHIFT 0 -#define TRBIDR_EL1_F BIT(5) -#define TRBIDR_EL1_P BIT(4) -#define TRBIDR_EL1_Align_MASK GENMASK(3, 0) -#define TRBIDR_EL1_Align_SHIFT 0 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1) #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 26da20f3ff40b..c585725172d51 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2319,3 +2319,16 @@ Sysreg TRBTRG_EL1 3 0 9 11 6 Res0 63:32 Field 31:0 TRG EndSysreg + +Sysreg TRBIDR_EL1 3 0 9 11 7 +Res0 63:12 +Enum 11:8 EA + 0b0000 NON_DESC + 0b0001 IGNORE + 0b0010 SERROR +EndEnum +Res0 7:6 +Field 5 F +Field 4 P +Field 3:0 Align +EndSysreg -- 2.30.2