From f1eb045639a38ae9ee80c466f81f2e18204f6d25 Mon Sep 17 00:00:00 2001 From: Duncan Ma Date: Tue, 1 Aug 2023 17:59:05 -0400 Subject: [PATCH] drm/amd/display: Fix dig register undefined [Why] Some of the stream encoder registers have register offset address 0. It is causing no display in some scenarios due to DIG_FE was not setup correctly and was not enabled. [How] Fix stream encoder register define list. Tested-by: Daniel Wheeler Reviewed-by: Charlene Liu Acked-by: Qingqing Zhuo Signed-off-by: Duncan Ma Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c index 957f39e1381b8..aa0c27e76e4e7 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c @@ -308,7 +308,7 @@ static const struct dcn31_apg_mask apg_mask = { }; #define stream_enc_regs_init(id)\ - SE_DCN32_REG_LIST_RI(id) + SE_DCN35_REG_LIST_RI(id) static struct dcn10_stream_enc_registers stream_enc_regs[5]; -- 2.30.2