From f66782cff479807ad7e98f0cf6a0c0babfe0159b Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Mon, 17 Jul 2023 19:35:11 +0200 Subject: [PATCH] dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy When the RK3568 PCIe v3 PHY supported has been upstreamed, RK3588 support was included, but the DT binding does not reflect this. This adds the missing bits. Reviewed-by: Conor Dooley Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20230717173512.65169-2-sebastian.reichel@collabora.com Signed-off-by: Vinod Koul --- .../bindings/phy/rockchip,pcie3-phy.yaml | 33 ++++++++++++++++--- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml index 9f2d8d2cc7a54..c4fbffcde6e40 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml @@ -13,19 +13,18 @@ properties: compatible: enum: - rockchip,rk3568-pcie3-phy + - rockchip,rk3588-pcie3-phy reg: maxItems: 1 clocks: - minItems: 3 + minItems: 1 maxItems: 3 clock-names: - items: - - const: refclk_m - - const: refclk_n - - const: pclk + minItems: 1 + maxItems: 3 data-lanes: description: which lanes (by position) should be mapped to which @@ -61,6 +60,30 @@ required: - rockchip,phy-grf - "#phy-cells" +allOf: + - if: + properties: + compatible: + enum: + - rockchip,rk3588-pcie3-phy + then: + properties: + clocks: + maxItems: 1 + clock-names: + items: + - const: pclk + else: + properties: + clocks: + minItems: 3 + + clock-names: + items: + - const: refclk_m + - const: refclk_n + - const: pclk + additionalProperties: false examples: -- 2.30.2