From f6b044e4d9fb3b2b00681c96a3fc438e9c281ef2 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Thu, 6 May 2021 19:19:29 +0300 Subject: [PATCH] drm/i915/adl_p: Require a minimum of 8 tiles stride for DPT FBs MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The specification only requires DPT FB strides to be POT aligned, but there seems to be also a minimum of 8 stride tile requirement. Scanning out FBs with < 8 stride tiles will result in pipe faults (even though the stride is POT aligned). Signed-off-by: Imre Deak Acked-by: Ville Syrjälä Reviewed-by: Mika Kahola Link: https://patchwork.freedesktop.org/patch/msgid/20210506161930.309688-10-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_fb.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index 927440ed14f48..29c558fbb397a 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -601,7 +601,11 @@ plane_view_dst_stride_tiles(const struct intel_framebuffer *fb, int color_plane, unsigned int pitch_tiles) { if (intel_fb_needs_pot_stride_remap(fb)) - return roundup_pow_of_two(pitch_tiles); + /* + * ADL_P, the only platform needing a POT stride has a minimum + * of 8 stride tiles. + */ + return roundup_pow_of_two(max(pitch_tiles, 8u)); else return pitch_tiles; } -- 2.30.2