From fd6435ea32d9243d116dbf50e7f1a8b33e01262b Mon Sep 17 00:00:00 2001 From: Vinod Govindapillai Date: Thu, 23 Mar 2023 13:44:26 +0200 Subject: [PATCH] drm/i915/reg: use the correct register to access SAGV block time Wrong register address is used to read the SAG block time. Fix the register address according to the bspec. Bspec: 64608 Signed-off-by: Vinod Govindapillai Reviewed-by: Stanislav Lisovskiy Signed-off-by: Stanislav Lisovskiy Link: https://patchwork.freedesktop.org/patch/msgid/20230323114426.41136-3-vinod.govindapillai@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3abfda4c7a3fa..f0f7b578b7269 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7740,7 +7740,7 @@ enum skl_power_gate { #define MTL_LATENCY_LEVEL_EVEN_MASK REG_GENMASK(12, 0) #define MTL_LATENCY_LEVEL_ODD_MASK REG_GENMASK(28, 16) -#define MTL_LATENCY_SAGV _MMIO(0x4578b) +#define MTL_LATENCY_SAGV _MMIO(0x4578c) #define MTL_LATENCY_QCLK_SAGV REG_GENMASK(12, 0) #define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700) -- 2.30.2