From ff85a7a9dedb6c876974ae20ff0c902a9247dae8 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 3 May 2022 00:41:24 +0200 Subject: [PATCH] ARM: dts: lan966x: add reset switch reset node Add the switch reset node which will later be used by the switch driver. The switch reset also resets the GPIO controller and the SGPIO controller, thus it also has to be connectected to these nodes. This way the reset will only issued once for the first device requesting the reset. Signed-off-by: Michael Walle Reviewed-by: Claudiu Beznea Tested-by: Horatiu Vultur Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220502224127.2604333-11-michael@walle.cc Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/lan966x.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index 786655b65dc53..238b4dfccaa22 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -391,6 +391,11 @@ status = "disabled"; }; + cpu_ctrl: syscon@e00c0000 { + compatible = "microchip,lan966x-cpu-syscon", "syscon"; + reg = <0xe00c0000 0x350>; + }; + can0: can@e081c000 { compatible = "bosch,m_can"; reg = <0xe081c000 0xfc>, <0x00100000 0x4000>; @@ -406,10 +411,20 @@ status = "disabled"; }; + reset: reset-controller@e200400c { + compatible = "microchip,lan966x-switch-reset"; + reg = <0xe200400c 0x4>; + reg-names = "gcb"; + #reset-cells = <1>; + cpu-syscon = <&cpu_ctrl>; + }; + gpio: pinctrl@e2004064 { compatible = "microchip,lan966x-pinctrl"; reg = <0xe2004064 0xb4>, <0xe2010024 0x138>; + resets = <&reset 0>; + reset-names = "switch"; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&gpio 0 0 78>; @@ -453,6 +468,8 @@ compatible = "microchip,sparx5-sgpio"; reg = <0xe2004190 0x118>; clocks = <&sys_clk>; + resets = <&reset 0>; + reset-names = "switch"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; -- 2.30.2